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2024 47th International Conference on Telecommunications and Signal Processing (TSP)

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Hardware parallel structure for convolution computing in image processing

A proposed hardware structure for convolution computing with application in image processing is described in this paper. The solution is based on using parallel processing in the computing of the filtering and MAC operation between the convolution mask and one or various filters, as well as on a proposed structured and defragmented input data. According to the described proposal, a flexible feature state of the proposed structure is possible with the combination of different parallelism computing types. Such feature can be extrapolated to different types of hardware. The parallel computing allows reduced computing time mainly in the filtering and convolution computing stages. The obtained structure is suitable to be implemented in convolutional neuronal networks applications.

Reyes Perez Melesio
Tecnologico National de Mexico en Celaya

Moises Arredondo-Velazquez
Meritorious Autonomous University of Puebla

Javier Diaz-Carmona
Tecnologico Nacional de Mexico en Celaya


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